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INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
* The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4020 14-stage binary ripple counter
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
FEATURES * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4020 are high-speed Si-gate CMOS devices and are pin compatible with the "4020" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns
74HC/HCT4020
The 74HC/HCT4020 are 14-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered parallel outputs (Q0, Q3 to Q13). The counter is advanced on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop.
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay CP to Q0 Qn to Qn+1 MR to Qn fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 11 6 17 101 3.5 19 15 6 19 52 3.5 20 ns ns ns MHz pF pF HCT UNIT
September 1993
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Philips Semiconductors
Product specification
14-stage binary ripple counter
PIN DESCRIPTION PIN NO. 8 10 11 16 SYMBOL parallel outputs ground (0 V) GND CP MR VCC
74HC/HCT4020
NAME AND FUNCTION
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 Q0, Q3 to Q13
clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) positive supply voltage
fpage
RCTR14
0 3
CT=0
CT
13
MGA829
9 7 5 4 6 13 12 14 15 1 2 3
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
FUNCTION TABLE INPUTS CP X Notes MR L L H OUTPUTS Q0, Q3 to Q13 no change count L
Fig.4 Functional diagram.
1. H = HIGH voltage level L = LOW voltage level X = don't care = LOW-to-HIGH clock transition = HIGH-to-LOW clock transition
Fig.5 Logic diagram.
Fig.6 Timing diagram.
September 1993
4
Philips Semiconductors
Product specification
14-stage binary ripple counter
DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay CP to Q0 propagation delay Qn to Qn+1 propagation delay MR to Qn output transition time +25 typ. 39 14 11 22 8 6 55 20 16 19 7 6 80 16 14 11 4 3 17 6 5 6 2 2 30 92 109 max. 140 28 24 75 15 13 170 34 29 75 15 13 100 20 17 100 20 17 65 13 11 4.8 24 28 -40 to +85 min. max. 175 35 30 95 19 16 215 43 37 95 19 16 120 24 20 120 24 20 75 15 13 4.0 20 24 -40 to +125 min. max. 210 42 36 110 22 19 225 51 43 110 22 19
74HC/HCT4020
TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.7
tPHL/ tPLH
ns
Fig.7
tPHL
ns
Fig.8
tTHL/ tTLH
ns
Fig.7
tW
clock pulse width HIGH or LOW
ns
Fig.7
tW
master reset pulse width 80 HIGH 16 14 removal time MR to CP maximum clock pulse frequency 50 10 9 6.0 30 35
ns
Fig.8
trem
ns
Fig.8
fmax
MHz
Fig.7
September 1993
5
Philips Semiconductors
Product specification
14-stage binary ripple counter
DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types
74HC/HCT4020
The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT CP MR
UNIT LOAD COEFFICIENT 0.85 1.10
AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH tW tW trem fmax propagation delay CP to Q0 propagation delay Qn to Qn+1 propagation delay MR to Qn output transition time clock pulse width HIGH or LOW 20 +25 typ. 18 8 22 7 7 8 2 47 max. 36 15 45 15 25 25 13 20 -40 to +85 min. max. 45 19 56 19 30 30 15 17 -40 to +125 min. max. 54 22 68 22 ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.7 Fig.7 Fig.8 Fig.7 Fig.7 Fig.8 Fig.8 Fig.7 UNIT V WAVEFORMS CC (V) TEST CONDITIONS
master reset pulse width 20 HIGH removal time MR to CP maximum clock pulse frequency 10 25
September 1993
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Philips Semiconductors
Product specification
14-stage binary ripple counter
AC WAVEFORMS
74HC/HCT4020
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency.
(1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8
Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time.
PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
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